Exemplary embodiments of the present invention relate to an apparatus for correcting a duty cycle of a clock signal.
Clock signals are widely used for adjusting an operational timing in various systems and circuits. While the clock signal is used inside of the systems and circuits, the clock signal is often delayed. It is important to correct the delay for securing a reliable operation. A delay locked loop (DLL) is generally used for compensating the delay of the clock signal.
FIG. 1 is a block diagram illustrating a conventional DLL.
The conventional DLL 100 includes a phase comparison unit 110, a delay control unit 120, a variable delay unit 130, a replica delay unit 140, and a locking detection unit 150.
The replica delay unit 140 delays an internal clock signal DLLCLK and outputs a feedback clock signal FBCLK. The internal clock signal DLLCLK is an output signal of the DLL. A delay amount of the replica delay unit 140 is obtained by modeling delays of delay elements to which the internal clock signal DLLCLK outputted from the DLL is inputted. The phase comparison unit 110 compares phases of an external clock signal EXTCLK and the feedback clock signal FBCLK and outputs an up/down signal UP/DN. The delay control unit 120 controls a delay amount of the variable delay unit 130 in response to the up/down signal UP/DN. The variable delay unit 130 delays the external clock signal EXTCLK by the delay amount controlled by the delay control unit 120 and outputs the internal clock signal DLLCLK. The locking detection unit 150 generates a locking signal LOCK indicating a locked state of the DLL based on the up/down signal UP/DN.
FIG. 2 is a block diagram illustrating a conventional duty cycle correction (DCC) circuit 200 for correcting a duty cycle of the clock signals.
The conventional DCC circuit 200 includes a phase splitter unit 210, a duty cycle ratio detection unit 220, and a duty cycle correction unit 230.
The phase splitter unit 210 generates a rising clock signal RCLK and a falling clock signal FCLK based on an output clock signal CLKOUT outputted from the DCC circuit. The rising clock signal RCLK is in phase with the output clock signal CLKOUT and the falling clock signal FCLK is out of phase, i.e., has the opposite phase, with respect to the output clock signal CLKOUT. For example, the rising clock signal RCLK is enabled as a logic high level during a period where the output clock signal CLKOUT has the logic high level and the falling clock signal is enabled as the logic high level during a period where the output clock signal CLKOUT has a logic low level.
The duty cycle ratio detection unit 220 detects the duty cycle ratio of the output clock signal CLKOUT by comparing enabling periods of the rising clock signal RCLK and the falling clock signal FCLK and outputs a duty cycle code CODE<0:N>.
The duty cycle correction unit 230 corrects a duty cycle of an input clock signal CLKIN inputted to the DCC circuit in response to the duty cycle code CODE<0:N> and outputs the output clock signal CLKOUT. The duty cycle correction unit 230 may adjust a slew rate of the input clock signal CLKIN or control a voltage level of the input clock signal CLKIN for correcting the duty cycle of the input clock signal CLKIN.
The DLL shown in FIG. 1 includes a plurality of delay units inside of the variable delay unit 130 for delaying the external clock signal EXTCLK to output the internal clock signal DLLCLK. The duty cycle of the external clock EXTCLK is changed by the variable delay unit 130. Therefore, the DCC circuit 200 shown in FIG. 2 is usually included in the DLL for correcting the duty cycle of the external clock signal EXTCLK.
If the DCC circuit 200 is coupled to an input terminal of the DLL 100, it is possible to provide the DLL 100 with the external clock signal EXTCLK having a relatively accurate duty cycle. However, the change in the duty cycle caused by the variable delay unit 130 is not corrected. Meanwhile, if the DCC circuit 200 is coupled to an output terminal of the DLL, it is possible to correct the changes in the duty cycle caused by the variable delay unit 130 but the duty cycle of the external clock EXTCLK inputted to the DLL is not corrected and, therefore, the internal clock signal outputted from the DLL has an inaccurate duty cycle. Accordingly, it is desirable for an exemplary embodiment of the present invention to design a circuit having a DCC circuit coupled to both the input terminal and the output terminal of a DLL in order to secure the correct duty cycle of the external clock signal EXTCLK. However, in this case, a solution is desirable where the size of the circuit including the DLL 100 and the DCC circuit 200 is not increased undesirably.